This invention relates to a nonvolatile semiconductor memory device, and particularly to a nonvolatile semiconductor memory device comprising a first read mode for performing a normal read operation and a second read mode for performing a read operation with lower power consumption than that of the first read mode.
A flash memory is a nonvolatile semiconductor memory device capable of holding the memorized content even if the power supply voltage is interrupted (see, for example, Japanese Patent Laid-Open No. 2004-127405 (patent document 1)). Flash memories are also being required to reduce power consumption in the wake of recent power saving trend and therefore a low-speed read mode, which is different from the normal read mode, is prepared in particular applications that require significant reduction of power consumption in the read operation, where data is read with a very low clock frequency that is different from the normal mode. In a microcomputer computer, for example, reduction of power consumption is required when the CPU reads program codes from the flash memory.
In such a flash memory, power consumptions by a charge pump circuit that generates an internal voltage higher than the external power supply voltage and by a reference voltage source that generates a reference voltage for reading are large.
With the conventional flash memory, however, there has been a problem that data cannot be read accurately when power consumption of a charge pump circuit or a reference current source is attempted to be reduced.
Therefore, a main object of the present invention is to provide a nonvolatile semiconductor memory device that can accurately read data with low consumption current.